Course syllabus
010113025-65 วงจรดิจิทัลและการออกแบบลอจิก (Digital Circuit and Logic Design)
Course Syllabus
Data entry : Asst.Prof. Dr.Ruslee Sutthaweekul
1. Course number and name
010113025-65 วงจรดิจิทัลและการออกแบบลอจิก (Digital Circuit and Logic Design)
2. Credits and contact hours
3(3-0-6)
3. Instructor’s or course coordinator’s name
Asst.Prof. Dr.Ruslee Sutthaweekul
Asst.Prof. Dr.Noppadon Chabgraw
Assoc.Prof.Chatchai Sermpongpan
4. Text book, title, author, and year
- Stephen Brown, Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design 3rd Edition, 2009, McGraw-Hill
- Enoch O. Hwang, Digital Logic and Microprocessor Design with VHDL, 2005, CL Engineering
5. Specific course information
- brief description of the content of the course (catalog description)
Introduction to digital signals; number systems and codes; digital circuits; logic gates and Boolean algebra; integrated circuit; logic families; TTL; CMOS; timing diagram; combinational circuits; sequential circuits; state diagram and implementation; microprocessor and microcontroller architecture; register and memory; timer/counter; basic input/output application, analog to digital conversion; serial interface; hardware description language; VHDL; digital circuit laboratory. - prerequisites or co-requisites
010113029-65 Computer Programming - indicate whether a required, elective, or selected elective (as per Table 5-1) course in the program
Required :
6. Specific goals for the course
- specific outcomes of instruction (e.g. The student will be able to explain the significance of current research about a particular topic.)
- CLO1 Understand the number systems and convert number systems.
- CLO2 Understand logical AND, OR, NOT, NAND, NOR, EX-OR, EX-NOR functions.
- CLO3 Identify a Boolean equation by using the truth table and shows its logic circuit and HDL.
- CLO4 Discuss the working principles of adder, decoder, encoder, multiplexer, demultiplexer.
- CLO5 Recognize the timing diagram, logic symbol and truth table of R-S, JK, D and T type flip-flops.
- CLO6 Designs and analyses the synchronous sequential circuits including Moore and Mealy models.
- CLO7 Recognizes the finite state machine diagrams.
- CLO8 Designs and analyses the dedicated microprocessors and applications.
- CLO9 Apply the knowledge to design digital circuits and to discuss digital problems relating electrical engineering field.
- explicitly indicate which of the student outcomes listed in Criterion 3 or any other outcomes are addressed by the course.
ABET Student Outcome (SO) Listed in Criterion 3 Course learning outcome (CLO) SO1 an ability to identify, formulate, and solve complex engineering problems by applying principles of engineering, science, and mathematics. - CLO1 Understand the number systems and convert number systems.
- CLO2 Understand logical AND, OR, NOT, NAND, NOR, EX-OR, EX-NOR functions.
- CLO3 Identify a Boolean equation by using the truth table and shows its logic circuit and HDL.
- CLO4 Discuss the working principles of adder, decoder, encoder, multiplexer, demultiplexer.
- CLO5 Recognize the timing diagram, logic symbol and truth table of R-S, JK, D and T type flip-flops.
- CLO6 Designs and analyses the synchronous sequential circuits including Moore and Mealy models.
- CLO7 Recognizes the finite state machine diagrams.
- CLO8 Designs and analyses the dedicated microprocessors and applications.
- CLO9 Apply the knowledge to design digital circuits and to discuss digital problems relating electrical engineering field.
7. Brief list of topics to be covered
| Week | Topic | Details | Activities |
|---|---|---|---|
| 1 | Design Concepts | ||
| 2 | Introduction to Logic Circuits | ||
| 3 | Number Representation and Arithmetic Circuits | ||
| 4 | Combinational-Circuit Building Blocks | ||
| 5 | Flip-Flops, Registers, Counters, and a Simple Processor | ||
| 6 | Synchronous Sequential Circuits | ||
| 7 | Dedicated Microprocessor |
8. Course Assessment
| Course assessment | Weight score (%) | Assessment tools | Date |
|---|---|---|---|
| midterm | 30 | midterm examination | 24 Jan 2026 |
| Final | 30 | final examination | 24 Mar 2026 |
| Assignment | 40 | assignment |
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